1. Field of the Invention
This invention relates to processes for manufacturing integrated circuits, and to a process for simultaneously fabricating bipolar and complementary field effect transistors ("BiCMOS") in a semiconductor substrate. More particularly, the invention relates to the fabrication of such devices having improved buried layers beneath N conductivity type wells in the epitaxial layer and to the fabrication of a completed BiCMOS structure using a minimal number of masks.
2. Description of the Prior Art
Bipolar and complementary metal conductor (CMOS) technologies have each been independently understood for many years. The ability to combine CMOS with bipolar on the same integrated circuit has raised new possibilities for very large scale integration. For example, bipolar output drivers may be employed with CMOS memories to provide more drive current. Because MOS slows down as temperature rises while bipolar speeds up, a CMOS bipolar combination may be employed to make devices less speed sensitive to temperature. Combining high performance bipolar devices with MOS transistors on the same integrated circuit allows a combination of the high-packing density of MOS devices with the high speed of bipolar and permits the integration of complex functions with high yields. The CMOS transistors with their inherently low power requirements have large noise margins, while the bipolar devices have an advantage in switching speed and greater current drive per unit area.
Accordingly, much effort has been devoted by process scientists and engineers toward methods of integrating bipolar and CMOS processes on a single wafer. Unfortunately, to date the resulting BiCMOS processes are generally not optimized for either the CMOS or the bipolar aspect, consisting instead of a brute force combination of the steps required to fabricate each type device. The result is often a lengthy and complicated process using a large number of masking operations, which is vulnerable to lower yields as a result of the complexity of the process. Typical prior art bipolar-CMOS processes are found in U.S. Pat. No. 4,484,388 to Iwasaki; U.S. Pat. No. 4,507,847 to Sullivan; and U.S. Pat. No. 4,536,945 to Gray et al.